A trend in the integrated circuit industry is to increase the functionality on a chip such that two or more types of transistor devices are produced on the same substrate. For instance, embedded DRAM or embedded SRAM involve the production of memory devices and logic devices on the same chip. Furthermore, the transistors for the logic component may consist of different functions such as an I/O device and a high performance device.
A typical transistor 10 is shown in FIG. 1 and is comprised of a substrate 1 with isolation regions 2 that separate transistor 10 from adjacent devices. A gate oxide layer 3 and a gate electrode 4 are formed on substrate 1. An ion implant is performed to generate lightly doped source/drain (LDD) regions 5. Spacers 6 are fabricated on the sidewalls of the gate electrode 4. Then a second ion implant is typically performed to produce heavily doped source/drain regions 7. The channel 8 is located beneath the gate electrode and between source/drain regions.
Each transistor device has a separate set of requirements or ground rules in order to optimize performance. The design typically includes a specific gate length, a width for the LDD regions, and a spacer width among other details. Devices with a narrow spacer width exhibit better performance (drive current) because of a lower series resistance. However, devices with larger spacer widths are better for short channel effect (SCE) control. Conventional fabrication methods only allow for one spacer width and therefore a compromise between performance and SCE control must be made. A better process is needed whereby up to three or more transistor devices on a substrate can be independently optimized for performance and SCE control.
A better drive current in transistor 10 can also be achieved by a smaller thickness of the gate electrode 4 which is commonly comprised of polysilicon. A smaller gate electrode thickness leads to improved drive current because of better polysilicon activation. Therefore, an improved process is needed with the flexibility to produce transistors with different gate electrode thicknesses in order to adjust the drive current and satisfy the device specifications.
Transistor devices on a wafer with different spacer widths are claimed in U.S. Pat. No. 6,344,398. One device has an oxide spacer adjacent to a gate while a second device has a nitride spacer on a gate covered by an oxide layer and a third device has no spacer. Although two different spacer widths are an improvement over conventional methods, additional flexibility such as provision for three or more spacer widths is desirable for advanced technologies.
In related art, U.S. Pat. No. 5,874,330 describes a method of forming different sidewall thicknesses on gate electrodes in cell and peripheral circuitry regions. A nitride layer is deposited on the gates and selectively removed from the peripheral regions. Then an oxide layer with a different thickness is deposited and etched back to afford an oxide sidewall in peripheral regions and an oxide layer over nitride sidewalls in cell regions.
U.S. Pat. No. 6,248,623 refers to embedded DRAM technology in which a three layer spacer consisting of a nitride layer between two oxide layers is formed. The spacer width in the memory cell region is different than the spacer width in the logic region. However, there is no provision to form two different spacer widths in the logic region.
U.S. Pat. No. 6,316,304 describes the formation of two different spacer widths on adjacent transistors. A stack comprised of a thin oxide layer, a nitride layer and a first oxide spacer layer is formed over adjacent gate electrodes. The first oxide spacer is selectively removed over one transistor and then a second oxide spacer layer is deposited. The oxide spacer layers are etched to produce a thinner spacer on the gate electrode that has only one oxide spacer layer thickness.